CAPPS: A Framework for Power-Performance Trade-Offs in On-Chip Communication Architecture Synthesis

On-chip communication architectures have a significant impact on the power consumption and performance of modern Multi-Processor System-on-Chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this technical report we present an automated framework (CAPPS) for fast system-level, application-specific, power-performance tradeoffs in bus matrix communication architecture synthesis. Our technical report makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macro-models into a bus matrix synthesis flow that enables designers to efficiently explore the powerperformance design space of different bus matrix configurations. Experimental results show that our energy macro-models incur less than 5% average cycle energy error across 180, 130 and 90nm technology libraries. Our early system-level power estimation approach also shows a significant speedup of as much as 2000X when compared with detailed gate-level power estimation. Furthermore, our bus matrix synthesis framework generates a tradeoff space with designs that exhibit an approximately 20% variation in power and 40% variation in performance for an industrial networking MPSoC application, demonstrating the usefulness of our approach. ∗ This research was partially supported by grants from SRC (2005-HJ-1330) and a CPCC fellowship. CAPPS: A Framework for Power-Performance Trade-Offs in On-Chip Communication Architecture Synthesis Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt Center for Embedded Computer Systems University of California, Irvine, CA {spasrich, younghwp, kurdahi, dutt}@uci.edu